? semiconductor components industries, llc, 2009 march, 2009 ? rev. 3 1 publication order number: nb3n551/d nb3n551 3.3 v / 5.0 v ultra-low skew 1:4 clock fanout buffer description the nb3n551 is a low skew 1 ? to 4 clock fanout buffer, designed for clock distribution in mind. the nb3n551 specifically guarantees low output ? to ? output skew. optimal design, layout and processing minimize skew within a device and from device to device. the output enable (oe) pin three ? states the outputs when low. features ? input/output clock frequency up to 180 mhz ? low skew outputs (50 ps typical) ? rms phase jitter (12 khz ? 20 mhz): 43 fs (typical) ? output goes to three ? state mode via oe ? operating range: v dd = 3.0 v to 5.5 v ? ideal for networking clocks ? packaged in 8 ? pin soic ? industrial temperature range ? these are pb ? free devices figure 1. block diagram clk q1 q2 q3 q4 oe device package shipping ? ordering information NB3N551DG soic ? 8 (pb ? free) 98 units/rail soic ? 8 d suffix case 751 marking diagrams* http://onsemi.com 1 8 3n551 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package 3n551 alyw 1 8 nb3n551dr2g soic ? 8 (pb ? free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. q4 gnd v dd oe i clk q1 q2 q3 pin connections 1 dfn8 mn suffix case 506aa 6k = specific device code m = date code = pb ? free package 6k m 14 nb3n551mnr4g dfn ? 8 (pb ? free) 1000/tape & reel (note: microdot may be in either location) 1 2 3 4 8 7 6 5 *for additional marking information, refer to application note and8002/d.
nb3n551 http://onsemi.com 2 table 1. oe, output enable function oe function 0 disable 1 enable table 2. pin description pin # name type description 1 i clk (lv)cmos/(lv)ttl input clock input. internal pull-up resistor. 2 q1 (lv)cmos/(lv)ttl output clock output 1 3 q2 (lv)cmos/(lv)ttl output clock output 2 4 q3 (lv)cmos/(lv)ttl output clock output 3 5 q4 (lv)cmos/(lv)ttl output clock output 4 6 gnd power negative supply voltage; connect to ground, 0 v 7 v dd power positive supply voltage (3.0 v to 5.5 v) 8 oe (lv)cmos/(lv)ttl input output enable for the clock outputs. outputs are enabled when high or when left open; oe pin has internal pull ? up resistor. three ? states outputs when low. ? ep thermal exposed pad (dfn8 only) thermal exposed pad must be connected to a sufficient thermal conduit. electrically connect to the most negative supply (gnd) or leave uncon- nected, floating open.
nb3n551 http://onsemi.com 3 table 3. maximum ratings symbol parameter condition 1 condition 2 rating units v dd positive power supply gnd = 0 v ? 7.0 v v i /v o input/output voltage t 1.5 ns ? gnd?1.5 v i /v o v dd +1.5 v t a operating temperature range, industrial ? ? ? 40 to +85 c t stg storage temperature range ? ? ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm soic ? 8 190 130 c/w c/w jc thermal resistance (junction ? to ? case) (note 1) soic ? 8 41 to 44 c/w ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm dfn8 dfn8 129 84 c/w jc thermal resistance (junction ? to ? case) (note 1) dfn8 35 to 40 c/w stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. jedec standard multilayer board ? 2s2p (2 signal, 2 power) table 4. attributes characteristic value esd protection human body model machine model > 4 kv > 200 v moisture sensitivity, indefinite time out of drypack (note 2) level 1 flammability rating oxygen index: 28 to 34 ul ? 94 code v ? 0 @ 0.125 in transistor count 531 devices meets or exceeds jedec standard eia/jesd78 ic latchup test 2. for additional moisture sensitivity information, refer to application note and8003/d.
nb3n551 http://onsemi.com 4 table 5. dc characteristics (v dd = 3.0 v to 3.6 v, gnd = 0 v, t a = ? 40 c to +85 c) (note 3) symbol characteristic min typ max unit i dd power supply current @ 135 mhz, no load, v dd = 3.3 v ? 20 40 ma v oh output high voltage ? i oh = ? 25 ma, v dd = 3.3 v 2.4 ? ? v v ol output low voltage ? i ol = 25 ma ? ? 0.4 v v oh output high voltage ? i oh = ? 12 ma (cmos level) v dd ? 0.4 ? ? v v ih, i clk input high voltage, i clk (v dd /2)+0.7 ? 3.8 v v il, i clk input low voltage, i clk ? ? (v dd /2) ? 0.7 v v ih, oe input high voltage, oe 2.0 ? vdd v v il, oe input low voltage, oe 0 ? 0.8 v zo nominal output impedance ? 20 ? rpu input pull ? up resistor, oe ? 220 ? k cin input capacitance, oe ? 5.0 ? pf ios short circuit current ? 50 ? ma dc characteristics (v dd = 4.5 v to 5.5 v, gnd = 0 v, t a = ? 40 c to +85 c) (note 3) symbol characteristic min typ max unit i dd power supply current @ 135 mhz, no load, v dd = 5.0 v ? 50 95 ma v oh output high voltage ? i oh = ? 35 ma 2.4 ? ? v v ol output low voltage ? i ol = 35 ma ? ? 0.4 v v oh output high voltage ? i oh = ? 12 ma (cmos level) v dd ? 0.4 ? ? v v ih, i clk input high voltage, i clk (v dd /2) + 1 ? 5.5 v v il, i clk input low voltage, i clk ? ? (v dd /2) ? 1 v v ih, oe input high voltage, oe 2.0 ? v dd v v il, oe input low voltage, oe 0 ? 0.8 v zo nominal output impedance ? 20 ? rpu input pull ? up resistor, oe ? 220 ? k cin input capacitance, oe ? 5.0 ? pf ios short circuit current ? 80 ? ma table 6. ac characteristics (v dd = 3.0 v to 5.5 v, gnd = 0 v, t a = ? 40 c to +85 c) (note 3) symbol characteristic conditions min typ max unit f in input frequency ? ? 180 mhz t jitter ( ) rms phase jitter (integrated 12 khz ? 20 mhz) (see figures 2 and 3) f carrier = 25 mhz f carrier = 50 mhz ? ? 43 16 ? ? fs t jitter (pd) period jitter (rms, 1 ) ? 2.0 ? ps t r /t f output rise and fall times; 0.8 v to 2.0 v ? 0.5 1.0 ns t pd propagation delay, clk to qn, 0 ? 180 mhz, (note 4) 1.5 3.0 6.0 ns t skew output ? to ? output skew; (note 5) ? 50 160 ps 3. outputs loaded with external r l = 33 ? series resistor and c l = 15 pf to gnd for proper operation. duty cycle out = duty in. a 0.01 f decoupling capacitor should be connected between v dd and gnd. a 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. 4. measured with rail ? to ? rail input clock. 5. measured on rising edges at v dd 2.
nb3n551 http://onsemi.com 5 figure 2. phase noise plot at 25 mhz at an operating voltage of 3.3 v, room temperature the above plot captured using agilent e5052a shows additive phase noise of the nb3n551 device measured with an input source generated by agilent e8663b. the rms phase jitter contributed by the device (integrated between 12 khz to 20 mhz; as shown in the shaded region of the plot) is 43 fs (rms jitter of the input source is 203.31 fs and output (dut+source) is 247.06 fs). figure 3. phase noise plot at 50 mhz at an operating voltage of 5 v, room temperature the above plot captured using agilent e5052a shows additive phase noise of the nb3n551 device measured with an input source generated by agilent e8663b. the rms phase jitter contributed by the device (integrated between 12 khz to 20 mhz; as shown in the shaded region of the plot) is 16 fs (rms jitter of the input source is 104.08 fs and output (dut + source) is 119.77 fs).
nb3n551 http://onsemi.com 6 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
nb3n551 http://onsemi.com 7 package dimensions dfn8 case 506aa ? 01 issue d notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 . 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. ??? ??? ??? ??? a d e b c 0.10 pin one 2 x reference 2 x top view side view bottom view a l (a3) d2 e2 c c 0.10 c 0.10 c 0.08 8 x a1 seating plane e/2 e 8 x k note 3 b 8 x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 2.00 bsc d2 1.10 1.30 e 2.00 bsc e2 0.70 0.90 e 0.50 bsc k 0.20 ??? l 0.25 0.35 1 4 8 5 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb3n551/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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